1. Field of the Invention
The present invention relates to a peel strength simulating apparatus for simulating peel strength between a semiconductor integrated circuit chip and a resin package which are bonded to each other, a peel strength simulating program storage medium in which a peel strength simulating program running on the peel strength simulating apparatus is stored, and a peel strength simulating method.
2. Description of the Related Art
Recently, as physical sizes of electronic instruments are reduced, physical sizes of semiconductor integrated circuit devices mounted on the electronic instruments are also reduced more and more. In such semiconductor integrated circuit devices, there is known a semiconductor integrated circuit device in which SCSP (Super Chip Size Package) having the size extremely close to the size of a semiconductor integrated circuit chip (silicon chip) is adopted. The SCSP type semiconductor integrated circuit device has a structure in which the semiconductor integrated circuit chip is exposed in a side face and a top surface of the semiconductor integrated circuit device while a resin package is formed below the semiconductor integrated circuit chip. When an excessive load due to temperature variation or a mechanical load is applied, sometimes there is generated a problem that the semiconductor integrated circuit chip and the resin package are peeled off each other at the boundary between the semiconductor integrated circuit chip and the resin package.
Therefore, conventionally, when the semiconductor integrated circuit device is mounted on the circuit board, the semiconductor integrated circuit chip and the resin package are fixed to each other by charging an under fill material between the resin package and the circuit board which are formed below the semiconductor integrated circuit chip, or the resin package is fixed by making a U-shaped groove in a lower surface of the semiconductor integrated circuit chip.
Japanese Patent Application Laid-Open (JP-A) No. 2000-40775 proposes a technique in which the peel generated at the boundary between the semiconductor integrated circuit chip and the resin package is prevented by providing a side-face coating portion for coating a part of outer peripheral side-face of the semiconductor integrated circuit chip in the resin package for sealing the circuit formed surface of the semiconductor integrated circuit chip.
JP-A No. 10-107182 proposes a technique in which a crack generated in the resin package by thermal stress is prevented by electrically connecting an electrode formed on the circuit board and the semiconductor integrated chip with a solder bump to regulate a size of a peripheral portion of sealing resin charged into a gap between the board and the semiconductor integrated circuit chip.
JP-A No. 2002-299547 proposes a technique in which the crack generated in the resin package by thermal stress is prevented by forming a tapered surface peripheral portion of one of first and second semiconductor integrated circuit chips having a larger contact area with the resin package, in the semiconductor integrated circuit device in which the outer peripheral portions of the first and second semiconductor integrated circuit chips mounted on the board in a laminated, manner is sealed by the resin package.
Thus, conventionally, the resin package and the circuit board are fixed by the under fill material in order to prevent the peel generated at the boundary between the semiconductor integrated circuit chip and the resin package. In this case, when the under fill material is not sufficiently charged, there is a fear that the peel is generated at the boundary between the semiconductor integrated circuit chip and the resin package after a reflow process, so that it is necessary to sufficiently manage a process of charging the under fill material. This causes a problem that production cost is increased. For the case where the U-shaped groove is made in the lower surface of the semiconductor integrated circuit chip, when the U-shaped groove made is not large enough, there is the fear that the peel is generated at the boundary between the semiconductor integrated circuit chip and the resin package, so that it is necessary to sufficiently manage a process of making the size of the under fill material. This also causes the problem that the production cost is increased.
Therefore, it is conceivable to employ the techniques proposed in JP-A Nos. 2000-40775, 10-107182, and 2002-299547are adopted. However, because the techniques proposed in JP-A Nos. 2000-40775, 10-107182, and 2002-299547 are a technique concerning a structure of the semiconductor integrated circuit device, the adoption of the techniques proposed in JP-A Nos. 2000-40775, 10-107182, and 2002-299547 requires the semiconductor integrated circuit device having the structure in which various conditions are considered to prevent the peel generated at the boundary between the semiconductor integrated circuit chip and the resin package. Accordingly, there is the problem that the cost is increased in the semiconductor integrated circuit device.